Semiconductor-On-Insulator (SeOI) and, in particular, Silicon-On-Insulator (SOI) semiconductor devices are of increasing interest in present and future semiconductor manufacturing, for example, in the context of the Complementary Metal Oxide Semiconductor (CMOS) technology.
Embedded DRAM devices become increasingly important for high-performance CMOS electronics, since compared to conventional SRAMs, the package density can be significantly increased. Besides the high integration, lower noise and power consumption, as well as higher bandwidth, can be achieved as compared to external SRAM/DRAM architectures. In addition, planar fully depleted SOT transistors represent a cost-effective approach with respect to the scaling of transistor devices. Planar fully depleted SOI transistors advantageously allow for back-biasing in order to adjust the threshold voltage to reduce leakage power and/or boost performances. With back bias, voltage threshold can be changed dynamically. Relatively thin buried oxide (BOX) layers, for example, with a thickness in the range of 5 to 50 nm, are necessary to provide optimal back-biasing benefit.
It is known to manufacture embedded DRAMs based on wafers with a pre-doped n-layer formed in the handle substrates, directly underneath the BOX and rather thick to contain the entire DRAM capacitor trench, typically several microns. For example, a phosphorous n+ layer with a concentration of 1019 cm−3 may serve as a capacitor bottom plate. The n+ layer is crucial in terms of scaling of the eDRAMs. However, there arises a problem when a logic part comprising back-biased planar fully or partially depleted SOL transistors shall be integrated together with embedded DRAMs, since the pre-doped n+ layer heavily hampers the manufacture of the back-biasing features. Back-bias regions must be electrically insulated one from another in order for them to be biased at different voltages without high leakage current. To achieve that insulation, we will need reverse-biased junctions on the current path from one back-bias region to another. We will typically have N and P layers on top of the handle substrate creating the need for junctions, and then cut vertically by STI structures to insulate one region from the others.
Such multilayer structures can potentially be manufactured starting with the thick N+ layer required for the eDRAM, but would require high implantation doses to be implanted through the SOI and BOX layers. This is not desirable because it might create defects and also dope the SOI layer.
In view of this, it is a problem underlying the present invention to provide a method for the integrated manufacture of both embedded DRAMS and back-biased transistors.